Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!pacbell!att!mtunx!alberta!oha!access!edm!steve
From: steve@edm.UUCP (Stephen Samuel)
Newsgroups: comp.arch
Subject: Re: Cretinous status/control register access (Was: Re: 80960 IO)
Message-ID: <3136@edm.UUCP>
Date: 16 Jun 88 06:12:05 GMT
References: <510@pcrat.UUCP>
Organization: Unexsys Systems, Edmonton,AB.
Lines: 24

From article <510@pcrat.UUCP>, by rick@pcrat.UUCP (Rick Richardson):
= 
= Finally, even with read/write registers in the chips, not all
= operations can be done with a (non-interruptible) "move", "and",
= or "or" instruction into the register.  Sometimes you have to
= read the old value from the register, "and" the value with a mask,
= then "or" in the new control bits, and then do your write
= back to the control register.  When you get this situation in
= combination with the "poor partitioning" problem, your only
= alternative is to shut off interrupts for this operation.  Many
= times I've wished that the processor implemented a non-interruptable
= read-and-or-write instruction.
Note that the 68020 has the (new) CAS (Compare And Swap) instruction which
allows what you want. It takes 2 registers and an address: R1= old value
R2=new value address=writ location. If location != R1 then set a condition
code, else write R2 to address. Although it is meant for software interlock
it's also real good for situations like you describe where you have to do
an interlocked update of a register when a simple AND/OR/MOV won't do.
 
 I believe that the '386 also has a similar instruction.
-- 
-------------
 Stephen Samuel 			Disclaimer: You betcha!
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