Path: utzoo!attcan!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!osu-cis!att!alberta!ubc-cs!grads.cs.ubc.ca!pajari
From: pajari@grads.cs.ubc.ca (George Pajari)
Newsgroups: comp.arch
Subject: Re: m88000 benchmarks
Keywords: FFT, m88000, benchmark, VLSI System Design
Message-ID: <3208@ubc-cs.UUCP>
Date: 16 Jun 88 21:38:45 GMT
References: <1941@pt.cs.cmu.edu>
Sender: nobody@ubc-cs.UUCP
Reply-To: pajari@grads.cs.ubc.ca (George Pajari)
Organization: UBC Department of Computer Science, Vancouver, B.C., Canada
Lines: 29

From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay) message <1941@pt.cs.cmu.edu>
> We don't have much benchmarking info yet about the Motorola 88000....
> The (compiler generated) code does 4 loads, 4 stores, 10 single precision
> float calculations, and 4 other things, in 27 clocks. At 20 MHz, that's
> 7.4 MFLOPS.

Don't believe it!

Although the benchmark shows both the C code and the assembler, the
assembler is NOT compiler generated, although you are supposed to draw
that conclusion!  (PS. it's 29 clocks, not 27).

When pressed at a local presentation on the M88000, Motorola reps conceded
that the 'infamous' FFT benchmark represented carefuly crafted HAND-CODED
RISC instructions ordered to take maximal advantage of the pipelining in
the 88100.  Furthermore, they admitted that the best code by any compiler
resulted in a 54 cycle loop...ALMOST TWICE THE LENGTH OF THE BENCHMARK CODE.

It would seem more resonable to call it about 3.5 MFLOPS.  (Impressive none
the less.)

Aren't MIPS/MFLOPS fun?  (And we thought Intel had the record for most cooked
benchmark figures in marketing literature.)


George Pajari
sometime grad student

(MIPS = Meaningless Indicator of Processor Speed)