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From: randys@mipon2.intel.com (Randy Steck)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <3587@omepd>
Date: 16 Jun 88 22:44:50 GMT
References: <291@wombat.UUCP> <22063@amdcad.AMD.COM> <6955@cit-vax.Caltech.Edu>
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Reply-To: randys@mipon2.UUCP (Randy Steck)
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In article <6955@cit-vax.Caltech.Edu> mangler@cit-vax.Caltech.Edu (Don Speck) writes:
>So the table is amended as follows:
>
>  Processor	    avg read	bus	bandwidth   VAX  MB/s:MIPS
>		     latency   width	available  "MIPS"  ratio
>25 MHz 88000	       45ns?   32+32	185 MB/s?    17     11?
>16 MHz MIPSco		?      32+32	120 MB/s?    10?    13?
>40 MHz RPM40	      100ns    32+16	240 MB/s     15     16
>25 MHz AMD 29000       80ns    32+32	170 MB/s     22      8
>

Another data point:
  Processor	    avg read	bus	bandwidth   VAX  MB/s:MIPS
		     latency   width	available  "MIPS"  ratio

20 MHz 80960           ?        32      53.3 MB/s    8       6.7

The ratio is so low because of the on-board instruction cache and the
existence of more complete addressing modes in the load/store
instructions.  The external address bus is a multiplexed bursting bus.
Performance degradation is about 7% for each wait state.  This contrasts
nicely with the 15-20% degradations and separate busses typically seen.

A better number to give for this table would be one that took into account
the bandwidth available from the internal instruction cache.
Unfortunately, this is a relatively difficult number to calculate and
really depends on the data/instruction access mix.  When I find some time,
I will try to do this for the Dhrystone benchmark.

Randy Steck
Intel Corp.      ...intelca!mipon2!randys