Path: utzoo!attcan!uunet!mcvax!ukc!reading!onion!cf-cm!mch
From: mch@computing-maths.cardiff.ac.uk (Major Kano)
Newsgroups: comp.arch
Subject: More On Write-Only Control Registers
Message-ID: <439@cf-cm.UUCP>
Date: 17 Jun 88 15:12:20 GMT
Reply-To: mch@computing-maths.cardiff.ac.uk (Major Kano)
Followup-To: comp.arch
Organization: University College Cardiff, Wales, United Kingdom
Lines: 21

In my earlier posting, I cannot have explained clearly what I meant. The few
replies that I saw/recieved suggested that there was no point in putting 
write-only or read-only registers at different addresses. 
Now that's all very well, but what I was trying to get at was why the **** have 
write-only control registers or read-only status registers AT ALL ?

I do not like the idea of not being able to read from a register that I've
written to. Maybe this is just paranoid and OS's should keep a copy ANYWAY
of whatever they load into a chip, but you can bet your next three pay checks
that SOMEDAY there will be a situation where a register must be read from;
eg., a faulty privileged program has used a chip before it was killed, and you
(the OS or super-user) have to know EXACTLY what it did.

Any comments ?

Regards,
-- 
Martin C. Howe, University College Cardiff | "Can YOU do the Milano Mosh ?"    
mch@vax1.computing-maths.cardiff.ac.uk.    |                                    
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These opinions are mine, but YOU can have them for just a few $$$ !