Path: utzoo!attcan!uunet!husc6!mailrus!ames!pasteur!ucbvax!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: RISC machines and scoreboarding
Message-ID: <22147@amdcad.AMD.COM>
Date: 18 Jun 88 22:46:49 GMT
References: <1082@nud.UUCP>
Reply-To: tim@delirun.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 27

In article <1082@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes:
|     On RISC processors without a scoreboard*, how are the results of memory
| references guaranteed to be available before they are used in subsequent
| computations?  I thought through several scenarios and couldn't find a very
| good solution and being being unfamiliar with RISCs other than the 88k,
| thought the net might have some answers.

The scoreboarding on the 88k (correct me if I'm wrong) associates a bit
for each register in the register file to tell whether the value is
stale or not.  During the issuing of an instruction, the operand
registers are checked for staleness, and the pipe is stalled if
required.

The bit-per-register is one way of detecting dependencies.  Another way
(used on the Am29000) is to associate a destination register pointer
(and a "ready bit") with each functional unit.  Forwarding logic matches
the register operand fields of the instruction being issued with the
destination register pointers of the functional units, stalling if it
finds a match and the value is not available, yet.  When the value is
available, it is forwarded to the correct operand bus (A or B, or
perhaps both) so that the instruction does not have to wait for the
value to be written into the register file.  This method has the benefit
of integrating closely with the forwarding logic.

	-- Tim Olson
	Advanced Micro Devices
	(tim@delirun.amd.com)