Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!ncar!noao!nud!rover!mph
From: mph@rover.UUCP (Mark Huth)
Newsgroups: comp.sys.amiga
Subject: Re: RISC 68K? (Was Re: Byte is rubbish - the Archimedes sure ain't !)
Message-ID: <780@rover.UUCP>
Date: 15 Jun 88 18:30:58 GMT
References: <489@nmtsun.nmt.edu> <10260013@eecs.nwu.edu>
Reply-To: mph@rover.UUCP (Mark Huth)
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 18

In article <10260013@eecs.nwu.edu> gore@eecs.nwu.edu (Jacob Gore) writes:
>/ comp.sys.amiga / daveh@cbmvax.UUCP (Dave Haynie) / Jun  8, 1988 /
>
>>There is a RISCy CPU set ... it claims to be fully object code compatible 
>>with the 68000.
>
>Me confused...  How can you have a RISC CPU that is object-compatible
>with a CISC CPU?

Well, the Edge machine is not a RISC machine.  It is a proprietary
gate-array implementation of the 68000 that runs with a faster clock.

RISC machines could be made object compatible with various CISC
processors by compiling the CISC object code into the RISC
instruction set.  The object wouldn't actually run, but a derivatiive
of the object could be produced.

Mark Huth