Path: utzoo!attcan!uunet!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga
Subject: Re: RISC 68K? (Was Re: Byte is rubbish - the Archimedes sure ain't !)
Message-ID: <4048@cbmvax.UUCP>
Date: 16 Jun 88 22:12:46 GMT
References: <780@rover.UUCP>
Organization: Commodore Technology, West Chester, PA
Lines: 52

in article <780@rover.UUCP>, mph@rover.UUCP (Mark Huth) says:
> In article <10260013@eecs.nwu.edu> gore@eecs.nwu.edu (Jacob Gore) writes:
>>/ comp.sys.amiga / daveh@cbmvax.UUCP (Dave Haynie) / Jun  8, 1988 /

>>>There is a RISCy CPU set ... it claims to be fully object code compatible 
>>>with the 68000.

>>Me confused...  How can you have a RISC CPU that is object-compatible
>>with a CISC CPU?

> Well, the Edge machine is not a RISC machine.  It is a proprietary
> gate-array implementation of the 68000 that runs with a faster clock.

Well I said RISCy.  That's because there is no absolute definition
of RISC.  RISC is to CPU architecture as Artifical Intelligence is
to Software architecture.  No one builds a pure RISC CPU, no one
builds a pure AI program, outside of perhaps pure theory.  And that's
because both RISC and AI are a collection of basic concepts, no a
single thing that can be easily defined.  I might use some RISC
concepts like pipelining, load/store instruction set, massive register
set, Harvard dual bus, scoreboarding, ~1 cycle/instruction, etc. in a CPU.
Many of these concepts existed before anyone ever said RISC.  Put a few
of 'em together in 1988 and someone calls it RISC.  Similarly, I might use 
hill climbing, AND/OR trees, heuristics, production systems, logical
inferencing, etc. in a program.  Many of these concepts existed before
anyone ever said AI, but put these together in a program in 1988 and
folks will say you're using AI.

As far as the Edge machine goes, it's got a lot of RISC ideas in it's 
architecture, which is why I called RISCy.  It claims 1.4 cycles per
instruction on an average, which is much closer to the 88000 than any
of the 680x0 family today.  It uses a Harvard architecture, with five
separate buses.  The 88000 uses a Harvard architecture, with two external
buses and 3 internal buses.  It uses two deep pipelines, much like the
88000.  It can even run in a multiprocessor setup, like the 88000. The
Edge 1200 claims 11 sustained MIPs, the 20MHz 88000 claims 12. In the
final analysis, though, the Edge machine looses.  It fills a whole board,
and systems start at $50,000.  The 88000 is a three chip set, and a 
system could probably be designed for $10,000.  They both run UNIX.

In fact, I always wondered by Edge bothered with 68010 compatibity.  It's
an interesting design study, and a good indication of what Motorola's
likely to be able to achieve with the 68040 and maybe beyond.  But you
don't need a compatible architecture to run UNIX.  I need one, 'cause I
want to run AmigaOS.  But I'll pay $50 for the CPU, or maybe even $100.
No more, please.

> Mark Huth
-- 
Dave Haynie  "The 32 Bit Guy"     Commodore-Amiga  "The Crew That Never Rests"
   {ihnp4|uunet|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
		"I can't relax, 'cause I'm a Boinger!"