Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!mailrus!tut.cis.ohio-state.edu!osupyr.mast.ohio-state.edu!vkr
From: vkr@osupyr.mast.ohio-state.edu (Vidhyanath K. Rao)
Newsgroups: comp.sys.amiga
Subject: Re: RISC 68K? (Was Re: Byte is rubbish - the Archimedes sure ain't !)
Summary: More silly ideas
Message-ID: <604@osupyr.mast.ohio-state.edu>
Date: 17 Jun 88 21:12:08 GMT
References: <780@rover.UUCP> <4048@cbmvax.UUCP>
Organization: Ohio State Math-Stats Dept
Lines: 25

Here are some of my silly musings on how to design a RISCy 68000 SOURCE
compatible chip i.e the assembler will eat 68000 assembly source, but will
NOT map it 1-1. In particular the multiply/divide will be replaced by
loops. (So your multiplication will interrepted by interrupts but should you
care?)

Here it comes: We have to live with the bit-twiddling and the plethora of
addressing modes on all the basic instructions. But we will try to get as
much parallelism as possible. The aim is to be like 6502: The extra memory
references must cost only one cycle each. In any case 68000 doesn't do
double indirection from memory so we don't have the throw-away cycles.
Of course the branches and jumps still cost too much. 

This leaves the interrupt service. I don't think that this can be changed.
So this is another pain we have to put up with.

The icing on the cake will be a big register cache so that subroutines etc
can just switch register windows.

There is a hidden cost: The instructions will be 1, 2, or 3 longwords long.
But we will NOT have 2^32 instruction/addressing mode combinations. There
may several different NOPs for example. Memory is cheap (he says).

Being somebody who couldn't build a slidepot based controller I don't
presume to say that this could be done. But would like it picked to pieces.
I have just donned my asbestos shields :-)