Path: utzoo!attcan!uunet!husc6!bloom-beacon!bu-cs!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!a.cs.uiuc.edu!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: m88000 benchmarks (and C vs ASM
Message-ID: <28200169@urbsdc>
Date: 29 Jun 88 14:27:00 GMT
References: <2434@winchester.mips.COM>
Lines: 21
Nf-ID: #R:winchester.mips.COM:2434:urbsdc:28200169:000:1044
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jun 29 09:27:00 1988


..> [Talking (I assume - the original note passed me by) about superoptimization]:
>Not so surprising for min and max (and minmax).  However, they require a
>sign extending shift, so that implementation is not possible on all
>machines.  Also, if a branch takes only one cycle (with delay slot),
		  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>you do not gain anything (in general).
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
>dik t. winter, cwi, amsterdam, nederland

You don't gain anything by avoiding branches if branches are cheap
- until the next generation of your machine comes by, more deeply
pipelined, with more expensive branches.

I've talked with representatives of several RISC manufacturers about
"the next generation" - I think MIPS was one of them, John Mashey can correct
me, and I know SPARC was. I keep asking "how many delay slots are you going
to need on your next generation". They say 2 - but to be backward compatible
they'll interlock, with the time delay for the interlock circuitry masked
by the delay slot.