Path: utzoo!attcan!uunet!husc6!mailrus!ames!ubvax!vsi1!wyse!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Superoptimiser. Message-ID: <2530@winchester.mips.COM> Date: 1 Jul 88 17:25:08 GMT References: <28200172@urbsdc> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 27 In article <28200172@urbsdc> aglew@urbsdc.Urbana.Gould.COM writes: > >> >Branches tend to be deadly to fast machines. Delay slots or no, it can still >> >give the cache/instruction stack indigestion. >>Gosh! You guys aren't thinking big enough. How about multiple >>parallel pipelines to compute all the various instruction threads >>in parallel and just keep the results of the one that is actually >>taken? Takes Big Bucks? Sure. But when you're using gallium >>arsenide, who cares? >The IBM 360 model 97 (I always get the model number wrong; >anyway, one of the early 360s) did this. 360/91, of which maybe (on the order of) 20 were built; there was also a 360/95 that was a little faster. It is instructive to examine this, compared with, for example, the 360/85, which was built at aboutthe same time (late 60s). The complexity of the 360/91 occurred because the CPU was too much faster than the memories. The 360/85 used a cache instead, was more cost-effective. Certainly the later machines derive more from its ideas than from the 91. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086