Path: utzoo!attcan!uunet!lll-winken!lll-lcc!pyramid!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Standard Un*x H/W architecture
Message-ID: <22407@amdcad.AMD.COM>
Date: 19 Jul 88 19:10:19 GMT
References: <980@garth.UUCP> <76700037@p.cs.uiuc.edu> <12005@ames.arc.nasa.gov>
Reply-To: tim@delirun.amd.com (Tim Olson)
Organization: Advanced Micro Devices
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In article <12005@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes:
| Finally, I understand that handling the IEEE gradual underflow
| behavior can add an extra cycle of latency.  I also have
| observed that the MIPS R2010 FPA (and maybe the new R3010 also)
| can do a floating add in 2 (!) clock cycles.  How did they do
| that?

By handling denormalized numbers with software traps, and by throwing a
lot of hardware at it!

-- 
	-- Tim Olson
	Advanced Micro Devices
	(tim@delirun.amd.com)