Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!amdahl!nsc!voder!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: HP2100 Origins
Message-ID: <14414@apple.Apple.COM>
Date: 21 Jul 88 17:19:19 GMT
References: <33895@yale-celray.yale.UUCP> <6310010@hpcupt1.HP.COM>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 26

[]

The original HP2116 was designed by a company that was bought by HP, I believe.
(Digital something-or-other, but not "Equipment Corp").
Its instruction set is a direct ripoff, in almost EVERY respect, of the PDP8.
The instruction word was extended to 16 bits, which gave an extra bit for
op-code, an extra bit for accumulator specification (it had 2), and 2 extra
bits for address offset. Like the PDP-8, it had no subtract instruction. You
had to negate and add. Like the PDP-8 it had an operate instruction. Unlike
the PDP8, it had two separate, identical shift fields, instead of a bit to
say shift twice. The I/O system is pretty similar.  And so on...

The original 2116 was built with CML logic, a kind of crude ECL. The 2116
ran very fast for its day; its sucessors were not as fast as the original.
The packaging was amazing- it could take a LOT of punishment, and keep on
ticking. This is part of the reason HP has a reputation for reliability.

The I/O system on the HP21xx was fairly simple; read or write, and strobe a
bit or two while you where at it. The I/O addresses were pre-decoded at each
slot; a six bit I/O address went through two 3->8 decoders, and these decoded
outputs were distributed to each card in an x-y matrix fashion, so an 'and'
gate on each card was sufficient for address recognition. Actually, two sets
of decoded addresses were distributed, so that a card could recognize two
consecutive addresses. This is so that complex I/O devices could occupy two
slots, but have the same address. This pre-decoded I/O scheme is what led to
the Apple II I/O structure.
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