Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!think!bloom-beacon!gatech!udel!rochester!pt.cs.cmu.edu!k.gp.cs.cmu.edu!lindsay
From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Fast FP addition
Keywords: Standard Un*x H/W architecture
Message-ID: <2342@pt.cs.cmu.edu>
Date: 21 Jul 88 17:29:28 GMT
References: <2626@quacky.mips.COM>
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 19

In article <2626@quacky.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>Yes, the R3010 also does IEEE 64-bit FP adds in 2 cycles.  Architecture,
>logic design, and circuit design of the R3010 are covered in a recent
>article in IEEE Micro:
>	C. Rowen et al., "The MIPS R3010 Floating-Point Coprocessor",
>	_IEEE Micro_, Vol. 8 No. 3, June 1988, pp. 53-62.

The article says "we chose a labor-intensive, hand-optimized design
methodology". It goes on to mention 25 man-years across 16 months, and
credits about 20 people.  Only two of those people were credited for
tooling - verification tools at that. Five people were credited with
drawing. 

Wouldn't a bigger tooling effort have been worth it?

-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science

"Imitation is not the sincerest form of flattery. Payments are."
- a British artist who died penniless before copyright law.