Path: utzoo!utgpu!water!watmath!clyde!att!pacbell!ames!mailrus!iuvax!pur-ee!a.cs.uiuc.edu!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Shifting question: m88k
Message-ID: <28200179@urbsdc>
Date: 21 Jul 88 14:09:00 GMT
References: <10186@tekecs.TEK.COM>
Lines: 23
Nf-ID: #R:tekecs.TEK.COM:10186:urbsdc:28200179:000:1043
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jul 21 09:09:00 1988


>..> Andrew Klossner talks about the 88K's bit field instructions:
>
>For the register-indirect version, rind is laid out as follows:
>
> bit:	 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
>	 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
>	+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>	|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|w|w|w|w|w|o|o|o|o|o|
>	+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>	 \_______________don't care________________/ \_width_/ \_offset/
>
>(The low ten bits of this register match the low ten bits of the direct
>form of the extract instruction.)
>
>  -=- Andrew Klossner   (decvax!tektronix!tekecs!andrew)       [UUCP]
>                        (andrew%tekecs.tek.com@relay.cs.net)   [ARPA]

Perhaps someone can answer what I see as one of the biggest
problems with the 88K: why weren't 6 bit fields provided for
the bit field instructions? It seems short sighted to design
an _architecture_ that is limited to 32 bits (as opposed to an
implementation).