Path: utzoo!utgpu!water!watmath!clyde!bellcore!rutgers!gatech!bloom-beacon!mit-eddie!uw-beaver!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.gwd.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: Re: Shifting question: m88k
Message-ID: <10190@tekecs.TEK.COM>
Date: 23 Jul 88 18:20:38 GMT
References: <10186@tekecs.TEK.COM> <28200179@urbsdc>
Sender: andrew@tekecs.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 24

[]

	"Perhaps someone can answer what I see as one of the biggest
	problems with the 88K: why weren't 6 bit fields provided for
	the bit field instructions? It seems short sighted to design an
	_architecture_ that is limited to 32 bits (as opposed to an
	implementation)."


The 88k shift (and all other ALU) instructions operate only on
registers.  Like other RISC architectures, its only instructions which
touch memory are load, store, and exchange.  Registers are fixed at 32
bits wide in the architecture.

To implement a double-register shift in a future chip, the "right"
approach would probably be to define a new instruction.  With the
current chip organization, such an instruction would necessarily take
multiple cycles because there aren't enough register ports to do it in
one cycle.  This would be the first multi-cycle "integer unit"
instruction, and I suspect it would bend the integer unit considerably
to fit it in.

  -=- Andrew Klossner   (decvax!tektronix!tekecs!andrew)       [UUCP]
                        (andrew%tekecs.tek.com@relay.cs.net)   [ARPA]