Path: utzoo!attcan!uunet!husc6!purdue!mailrus!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Cray & Amdahl (Was: missing Dhrystone 2.1)
Message-ID: <12332@ames.arc.nasa.gov>
Date: 26 Jul 88 03:24:09 GMT
References: <4232@cbmvax.UUCP> <76700035@p.cs.uiuc.edu> <5342@june.cs.washington.edu> <60952@sun.uucp> <7819@hall.cray.com>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 23

In article <7819@hall.cray.com> blu@hall.UUCP (Brian Utterback) writes:

>Cray's continue to use only physical memory rather than virtual for one reason:
>it's faster.  That's our charter: faster.

Help!  I have looked in my trusty computer architecture books (latest is
5 years old) and can find very little on just how much complexity (number
of gates, real estate on or off chip, etc.) various architectural features
consume.  Now, I suppose that since the whole world is interested in "RISC"
these days, there must be a whole slough of books out there which give such
information so that correct trade-offs can be made.  I would like to know
how much space a 16 entry MMU consumes versus an adder with bounds checking.
And also, how many gates deep the critical path is for each.  And so on.
None of my hardware books have anything more than the cost of several
simple adders.  Any suggestions on more recent books that contain good
information of this type?


-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117