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From: gillies@p.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: Cray & Amdahl (Was: missing Dhrysto
Message-ID: <76700040@p.cs.uiuc.edu>
Date: 26 Jul 88 18:08:00 GMT
References: <5342@june.cs.washington.edu>
Lines: 29
Nf-ID: #R:june.cs.washington.edu:5342:p.cs.uiuc.edu:76700040:000:1267
Nf-From: p.cs.uiuc.edu!gillies    Jul 26 13:08:00 1988


In my undergrad systems course we learned to optimize a multi-level
memory design for speed, given a constant number of $$$.  We used:

1.  Paper & pencil
2.  Simple model of cacheing/paging hit ratio versus cache size (often
    some given linear function  hitsRate = f(memorySize)).
3.  The price/performance of various kinds of memory, for each kind:
    a.  $/K
    b.  access time

For a 2-level memory system (main memory, cache), you could plot a
2-dimensional curve (main memory size versus cache size), then derive
the highest performance point on the curve.

Of course, this analysis is impossible if you don't know your
instruction mix and software paging patterns.  And if the customer
wants to expand main memory, he should probably expand the cache at
the same time (I think this is uncommon).  So I doubt many companies
pay attention to this analysis -- maybe it's mostly academic.

My point is that it's an optimization problem, which if
oversimplified, can even be handled with paper & pencil.  If not, then
it can probably be solved by nonlinear optimization methods.


Don Gillies, Dept. of Computer Science, University of Illinois
1304 W. Springfield, Urbana, Ill 61801      
ARPA: gillies@cs.uiuc.edu   UUCP: {uunet,ihnp4,harvard}!uiucdcs!gillies