Path: utzoo!yunexus!geac!daveb
From: daveb@geac.UUCP (David Collier-Brown)
Newsgroups: comp.arch
Subject: Re: memory system design
Message-ID: <3106@geac.UUCP>
Date: 29 Jul 88 15:51:47 GMT
Article-I.D.: geac.3106
References: <483@m3.mfci.UUCP>
Organization: GEAC Computers, Toronto, CANADA
Lines: 28


 In article <76700040@p.cs.uiuc.edu> gillies@p.cs.uiuc.edu writes:
| In my undergrad systems course we learned to optimize a multi-level
| memory design for speed, given a constant number of $$$.  
| [...]
| For a 2-level memory system (main memory, cache), you could plot a
| 2-dimensional curve (main memory size versus cache size), then derive
| the highest performance point on the curve.
 
 
From article <483@m3.mfci.UUCP>, by colwell@mfci.UUCP (Robert Colwell):
|  You can solve anything if you oversimplify it enough.  I have my
|  doubts as to whether you'd EVER get anything useful out of this
|  approach in the real world.  You have to 

  Assuming you can't (ever?) get representative workloads, the method above
still gives you a bound on memory speed for a given design/cost.
That alone is a very powerfull tool.  

--dave c-b
ps:  This kind of back-of-envelope calculation is commonly used to
throw out too-cheap configurations proposed by salespersons for
well-known "low bid" companies.
-- 
 David Collier-Brown.  {mnetor yunexus utgpu}!geac!daveb
 Geac Computers Ltd.,  |  Computer science loses its
 350 Steelcase Road,   |  memory, if not its mind,
 Markham, Ontario.     |  every six months.