Path: utzoo!utgpu!attcan!uunet!convex!killer!ames!ucsd!rutgers!uwvax!oddjob!uxc!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Self-modifying code (and bitblt
Message-ID: <28200183@urbsdc>
Date: 29 Jul 88 16:03:00 GMT
References: <308@laic.UUCP>
Lines: 40
Nf-ID: #R:laic.UUCP:308:urbsdc:28200183:000:1809
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jul 29 11:03:00 1988


..> Talk about capabilities?

Why has no-one mentioned one of the biggest problems with
capability based systems? The security people who evaluate
and classify secure _systems_ (C2, B1, etc., Gould knows
about them) don't like "OS in hardware" or "OS in microcode"
because then they have to understand the microcode/microarchitecture,
and there's more of it to understand than in a conventional system.
Plus the fact that capability inheritance rules have never
been satisfactorily modeled and shown to be secure (I'm sure
that I'll receive flames about that, eh? :-)

***************************************************************
Attempting to break out of the C vs ASM and HW vs SW BLT morass
***************************************************************

I notice Bob Colwell from Multiflow is a regular reader.
Just read the IEEE Transactions on Computers article on 
Multiflow's TRACE machines. 

    Questions: Exactly how does the store register file
on the floating point subsystem operate?
    You mention that there are only 8 32 bit busses across
the board edge. Exactly what are they? Are there more busses
in the system, but only a subset to any board? Are address
and data busses split? Etc.
    Everybody I know who has a reason to know the details of
the TRACE says that it is loaded down with crossbars. How and
where?


Andy "Krazy" Glew. Gould CSD-Urbana.    1101 E. University, Urbana, IL 61801   
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