Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!nosc!ucsd!ucbvax!decwrl!labrea!glacier!jbn
From: jbn@glacier.STANFORD.EDU (John B. Nagle)
Newsgroups: comp.lang.forth
Subject: Re: Novix/Harris FORTH chip
Message-ID: <17595@glacier.STANFORD.EDU>
Date: 31 Jul 88 23:42:58 GMT
References: <8807251832.AA03400@jade.berkeley.edu> <1534@crete.cs.glasgow.ac.uk> <3385@juniper.uucp>
Reply-To: jbn@glacier.UUCP (John B. Nagle)
Organization: Stanford University
Lines: 18


     It is a fascinating part.  I've seen the Novix version with the Computer
Cowboys software (a joke), but apparently the Harris version is OK.  It's
worth thinking about the implications of the architecture.  There are three
separate memory systems, a main one and two specialized ones for the return
stack and the data stack, and all can cycle on every CPU cycle.  This
simplifies the architecture considerably.  Something similar was tried
with the National Semiconductor PACE chip in the early 1970s, but, like
most National Semi micros, it never really caught on.  The PACE had a
hard limit of ten subroutine calls in depth, and that wasn't enough.
Memory is cheaper now.

     It's nice that the chip has so few gates, but it has an awful lot
of pins.  Those three memory paths are a problem.  It really needs to
be reimplemented as an ASIC with on-chip RAM for the stacks, which would
make for a more convenient chip, and one more useful in, say, microcontroller
applications.  Did Harris do it that way?

					John Nagle