Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!rutgers!ucsd!ucbvax!lynx.northeastern.EDU!tmetro From: tmetro@lynx.northeastern.EDU Newsgroups: comp.sys.apple Subject: Re: Benchmarks - Even on a Zip Chip Message-ID: Date: 25 Jul 88 02:00:59 GMT Sender: daemon@ucbvax.BERKELEY.EDU Organization: The Internet Lines: 56 Gary Snow writes: > Here are some comparision benchmarks done on various Apple Computers. > The 3.6mhz machine is equiped with an Accelerator //e. > > Computer Speed Basic Time1 Time2 Time3 > ----------- ---------------- ----------------------- ----- ----- ----- > Apple //e 1.0MHz 65C02 ProDOS Basic 1.1-40col 7:38 2:20 4:44 > Apple //e 1.0MHz 65C02 ProDOS Basic 1.1-80col XXXXX XXXXX 7:29 Accelerator: > Apple //e 3.6MHz 65C02 ProDOS Basic 1.1-40col 2:21 0:43 2:52 > Apple //e 3.6MHz 65C02 ProDOS BAsic 1.1-80col XXXXX XXXXX 5:14 Zip Chip: > Apple //e 4.0MHz 65C02 ProDos Basic 1.1-40col 2:24 0:43 3:11 > Apple //e 4.0MHz 65C02 ProDos Basic 1.1-80col XXXXX XXXXX 5:46 > Apple //gs 2.8MHz 65C816 ProDOS Basic 1.1-40col 2:50 0:51 2:03 > Apple //gs 2.8MHz 65C816 ProDOS Basic 1.1-80col XXXXX XXXXX 3:20 > From the looks of it the Zip Chip is not quite up to Snuff with the > good old Accelerated //e, because it lost in both the prime number > seive and the printing seive, and only tied in the counting sieve... > tsk tsk tsk. > UUCP:[ihnp4 cbosgd hplabs!hp-sdd sdcsvax nosc]!crash!pnet01!pro-sol! > megaquark > ARPA:crash!pnet01!pro-sol!megaquark@nosc.mil > INET:megaquark@pro-sol.cts.com The author of the message forgot to list "ZipChip" in place of "65C02" where it was used. I guess all the 4.0MHz specs are for a ZipChip. The differences may be due to the size of the cache RAM used in each implementation. In the case of the accelerator card it has 256K of fast RAM to work with - used both for the BASIC loop and a copy of the BASIC ROMs. The Zip Chip probably doesn't have enough cache RAM to hold both the BASIC loop and the ROM code that it accesses, so it probably has to slow to 1Mhz to fetch a few bytes each time through the loop. A chip similar to the Zip Chip (using cache RAM within the CPU package) is being developed that will run at 8Mhz. It will be based on a Western Design 8MHz W65C02. There is a 65C816 version for the //gs in the works too. ___________ / Tom Metro \_____________________________________________________________ | _ _ | | INET: tmetro@pro-angmar.uucp --/\/\_| |_| '- DigiTell, Inc. | | ARPA: crash!pnet01!pro-angmar!tmetro@nosc.mil Newton, MA | | UUCP: [ihnp4 sdcsvax nosc]!crash!pnet01!pro%angmar!tmetro | |_Alternate: tmetro@lynx.northeastern.edu__________________________________| "The Ghost crowd supports me. They're "BOO"-ing you!" -Hobbes