Xref: utzoo comp.sys.intel:480 comp.sys.ibm.pc:17347
Path: utzoo!attcan!uunet!mcvax!enea!tut!jja
From: jja@tut.fi (Ahola Jari)
Newsgroups: comp.sys.intel,comp.sys.ibm.pc
Subject: Re: Raiders of the lost opcodes of the 80386
Message-ID: <4299@korppi.tut.fi>
Date: 19 Jul 88 16:17:38 GMT
References: <4071@korppi.tut.fi> <4814@killer.UUCP>
Organization: Tampere University of Technology, Finland
Lines: 34

In article <4814@killer.UUCP>, richardh@killer.UUCP (Richard Hargrove) writes:
> 
> First, these mnemonics are not documented in Intel's _80386 Programmer's 
> Reference Manual_. I checked both chapter 17, "80386 Instruction Set",
> and Appendix A, Opcode Map. So my question is: What opcodes are supposed to
> be the correct ones for the above instructions? 
> 

Yes, I know that: These opcodes are mentioned on 386's datasheet dated
may -86. The opcodes for these were:

	XBTS	0F A6 mod reg  r/m  (total 3 bytes)+ 2 (386 addr. mode)	
	IBTS    0F A7 mod reg  r/m               -//-

danno@microsof told me the following: (thanks to you danno)

To: uunet!tut!jja
Subject: Re: Raiders of the lost opcodes of the 80386
In-reply-to: your article <4071@korppi.tut.fi>

I don't know Microsoft's position, but I know that Intel no longer
supports the op-codes.  It turns out that it is faster to do the
same thing using the double-precision shift instructions.

The technique is detailed in the "80386 Programmer's Manual", order
number 230985-001.

-jja

-- 
Jari 'jja' Ahola	| Tampere University of Technology, CS dept.
Opiskelijankatu 16 A 12 | P.O. Box 527, 33101 Tampere, Finland
33720 Tampere 		| Tel (intl) 358 31 162708 (work)/358 31 174009 (home)
Finland. Puh. 931-174009| Net address: jja@tut (UUCP)  AHOLA@FINTUTA (BITNET)