Xref: utzoo comp.arch:5672 comp.sys.nsc.32k:395
Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!vsi1!daver!wombat!george
From: george@wombat.UUCP (George Scolaro)
Newsgroups: comp.arch,comp.sys.nsc.32k
Subject: Re: Big sieve results for SUN3 & SUN4
Keywords: integer benchmark
Message-ID: <298@wombat.UUCP>
Date: 22 Jul 88 05:56:22 GMT
References: <517@pcrat.UUCP> <2294@sugar.UUCP> <1662@gofast.camcon.uucp>
Reply-To: george@wombat.UUCP (George Scolaro)
Organization: Assn. for the prevention of Polar Bears and Kangaroos
Lines: 38

And for some of the newer CISC machines (the NS32532), here are the numbers.

This was run on a PC add-in card with a 20 Mhz 32532, running 4 wait states
(fast rams are expensive right now, I'll post the faster 1 wait state timing
at a later date).

In article <1662@gofast.camcon.uucp> anc@camcon.uucp (Adrian Cockcroft) writes:
>In article <2294@sugar.UUCP>, karl@sugar.UUCP (Karl Lehenbauer) writes:
>> 
>> 		Array size	20000	40000
>>     Machine 	 (bytes)	 time (secs)
	NS32532@20 Mhz 4ws	 0.47	 0.95
>        SUN 4/110 (7 MIPS)      0.61    1.23
>        SUN 3/260 (4 MIPS)      0.96    1.94
>> 	Turbo-Amiga		1.14	2.32
>> 	VAX 8600		1.19	2.64
>> 	VAX-11/780		3.04	6.38
>> 	Amiga			5.68	11.50
>> 	VAX-11/750		6.11	13.13
>> 	IBM PC AT		8.13	99.71
>

For those not familiar with the NS32532, it is a continuation of the
Series 32000 processors from National Semiconductor. Most instructions
are 2 clocks, giving a maximum performance of 15 native MIPS at 30 Mhz.
A four stage pipeline allows address computation in parallel with
instruction execution, and the read-ahead/write-behind logic pemits
memory-to-memory operations at almost full instruction execution rate.

The sieve was compiled with the CTP compilers from National, and this
was not a bogus time - no instructions were "optimized out".

More numbers as we get them...

George Scolaro & Dave Rand
george@wombat	 dlr@daver.uucp

(try {pyramid|sun|vsi1|killer}!daver!dlr
			      !daver!wombat!george)