Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-tis!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Split I and D caches and IBM lawyers
Keywords: IBM, patents, Harvard architecture
Message-ID: <12718@ames.arc.nasa.gov>
Date: 2 Aug 88 15:44:14 GMT
References: <62370@sun.uucp>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 20

In article <62370@sun.uucp> dre%ember@Sun.COM (David Emberson) writes:
>
>Now that IBM has supposedly "invented" Harvard architecture with cache
>memories, I think it would be interesting to try to list machines that used
>this "new" technique prior to IBM's lawyers laying claim to it.  I know that
>I worked on designs at Prime that had separate I and D caches as early as
>1978.  But none of these made it out of the lab, at least that I am aware of.

Of course, the CDC 6600 didn't use a D-cache, but it did have an I-cache
back in 1964 that was separate from the processor-memory data path.  I
wonder if Cray patented this concept?  (The cache on the 6600 was not
quite randomly addressable, so does that make it not a cache?)

It is perfectly clear that "RISC" is not a patentable concept, but there
may be some real patents somewhere in that list.  

-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117