Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!claris!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: Split I and D caches and IBM lawyers
Message-ID: <15086@apple.Apple.COM>
Date: 2 Aug 88 17:23:54 GMT
References: <62370@sun.uucp>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 50

[]
>In article <62370@sun.uucp> dre%ember@Sun.COM (David Emberson) writes:
>
>Now that IBM has supposedly "invented" Harvard architecture with cache
>memories, I think it would be interesting to try to list machines that used
>this "new" technique prior to IBM's lawyers laying claim to it.

The IBM patent itself has a list of prior art, together with explanations of
the differences. You have to be very careful about reading just exactly
what they are claiming. Claim No.1 says basically: Separate I & D caches,
with tag stores, and valid bits settable under program or system control.
The relevant differences are the "settable under program control" part,
i.e. they have cache control instructions. To continue:
 Claim 2: #1+Both caches can be accessed simultaneously, but cache<->main mem.
path only allows one at a time.
 Claim 3: #1+Dirty bit, settable under program or system control (more insts.!)
 Claim 4: #3+Data cache can write back to mem, but not Icache.
 Claim 5: #4+means for changing the valid bit checks the Icache tags
 Claim 6: #5+Forward data directly to CPU on miss (as well as sending to cache)
 Claim 7: #5+Means for inhibiting the setting of the dirty bits (more insts.!)
 Claim 8: #7+2 way set assoc. with LRU bit to determine which set
 Claim 9: #8+bit is set to indicate LRU on hit or miss
 Claim 10:#9+don't update tags if hit occurs, but valid bit is off.
 Claim 11:#10+tag store is faster than data store.
 Claim 12: 2 Caches w/tag+data sections, valid bit/line, settable by sys/prog,
            >=1 dirty bit/line, settable by sys/prog, no write path from Icache
            to main mem
 Claim 13:#12+Forward data directly to CPU on miss (as well as to cache)
 Claim 14:#13+means for preventing setting of the dirty bit
 Claim 15:#14+ each cache is 2 way set assoc. w/LRU
 Claim 16:#15+don't update tags if hit occurs, but valid bit is off.

I may have missed the emphasis of the claims in paraphrasing them, but I
believe the thrust is that there is no hardware to ensure that writes to the
DCache get reflected in the Icache, and there are cache control instructions.

The disclosure lists 6 cache control instructions:
 Set Data Cache Line: write tag, but don't actually fetch data; this line will
                used for temp storage, and you don't care what prev. data was.
 Invalidate Data Cache Line: force susequent accesses to go to main mem.
 Invalidate Inst Cache Line: ditto
 Store Data Cache Line: make sure main mem has valid copy
 Load  Data Cache Line: prefetch? don't forward to CPU!
 Store & Synch. Data Cache Line: make sure main mem has valid copy, don't start
                new inst. until this completes

In summary: IBM patents are not without foundation. They are diligent about
researching prior art. The patents are strong, well written patents, and do
not make wild claims about inventing fundamental concepts (unless, of course,
they actually did, which is not an uncommon case).
--
{decwrl,hplabs,ihnp4}!nsc!apple!baum		(408)973-3385