Path: utzoo!utgpu!attcan!uunet!steinmetz!nuke!oconnor
From: oconnor@nuke.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: Split I and D caches and IBM lawyers
Message-ID: <11717@steinmetz.ge.com>
Date: 3 Aug 88 13:14:51 GMT
References: <62370@sun.uucp>
Sender: news@steinmetz.ge.com
Reply-To: oconnor%sungod@steinmetz.UUCP
Organization: GE Corporate R&D Center
Lines: 59

I don't know when IBM filed their patent application, but
as of October 1968, the following were published "prior art"
( We at GE published them as a goverment contract final report )

An article by baum@apple.UUCP (Allen Baum) says:
] The IBM patent itself has a list of prior art, together with explanations of
] the differences. You have to be very careful about reading just exactly
] what they are claiming. Claim No.1 says basically: Separate I & D caches,
] with tag stores, and valid bits settable under program or system control.
] The relevant differences are the "settable under program control" part,
] i.e. they have cache control instructions. To continue:

The RPM40 I-Cache has cache control instructions, including loading
and storing tags and their valid bits. ( If you're going to
software manage the cache, you have to be able to save and restore
it's context, at least the part you manage, on task switches. )

]  Claim 2: #1+Both caches can be accessed simultaneously, but
]  cache<->main mem. path only allows one at a time.

This was part of a proposal GE submitted to the Government in late '86

]  Claim 4: #3+Data cache can write back to mem, but not Icache.

This was part of the final report.

]  Claim 6: #5+Forward data directly to CPU on miss as well as sending to cache

This is exactly how our I-Cache works, and is part of the October '86 report.

]  Claim 11:#10+tag store is faster than data store.

No kidding. Is this new ? It wasn't to us in October of 1986.

]  Claim 13:#12+Forward data directly to CPU on miss (as well as to cache)

Hey I've seen this claim before ! This was part of the Oct.'86 final report.

] I may have missed the emphasis of the claims in paraphrasing them, but I
] believe the thrust is that there is no hardware to ensure that writes to the
] DCache get reflected in the Icache, and there are cache control instructions.

"cache control instructions" were part of our Icache in the final report.

] In summary: IBM patents are not without foundation. They are diligent about
] researching prior art. The patents are strong, well written patents, and do
] not make wild claims about inventing fundamental concepts (unless, of course,
] they actually did, which is not an uncommon case).

"prior art" is almost impossible to be current on, in a field moving
as fast as computer architecture. The date of filing of the IBM
patents is very important. When were they filed ?

] {decwrl,hplabs,ihnp4}!nsc!apple!baum		(408)973-3385


--
 Dennis O'Connor   oconnor%sungod@steinmetz.UUCP  ARPA: OCONNORDM@ge-crd.arpa
    "Never confuse USENET with something that matters, like PIZZA."