Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!vsi1!wyse!mips!earl
From: earl@mips.COM (Earl Killian)
Newsgroups: comp.arch
Subject: separate integer and float registers
Message-ID: <2724@wright.mips.COM>
Date: 6 Aug 88 00:31:02 GMT
Lines: 25

I thought I had posted this a while ago, but it appears not have have
made it.

I have a question for the Motorola folks in the crowd: what were the
tradeoffs that went into the decision to make the floating point and
integer registers the same?

Before micros, there was about an even split between architectures
with separate fp registers and those without.  Then came micros and
their architectures, where the floating point registers were always
separate because they were on different chips.  Finally as it is
becoming feasible to put cpu and fpu on the same chip, the question
becomes relevant again.  It is interesting that one of the first such
chips, the 88100, choose to take advantage of 1-chipness and combine
the register files.  Why?

How is the 88100's register file organized?  Is it a 2x32 read, 1x32
write?  2x64 read, 1x64 write?  Or something else?  I'm guessing from
the fact that the repeat rate for double-precision fp ops is a new one
every 2 cycles that it is 2x32, so it takes 2 cycles to read the
operands and 2 cycles to write the results.  Is that right?  Does that
mean that after a fadd you must wait a cycle before starting an
integer instruction, because the register file is in use?
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