Path: utzoo!attcan!uunet!swlabs!jack
From: jack@swlabs.UUCP (Jack Bonn)
Newsgroups: comp.arch
Subject: Re: VAX Memory Test
Message-ID: <1743@swlabs.UUCP>
Date: 6 Aug 88 01:00:38 GMT
References: <3300032@m.cs.uiuc.edu> <12849@mimsy.UUCP>
Reply-To: jack@swlabs.UUCP (Jack Bonn)
Organization: Software Labs, Ltd. Easton, CT USA
Lines: 22

In article <12849@mimsy.UUCP> chris@mimsy.UUCP (Chris Torek) writes:
>The easiest test for a Vax with ECC is to let the machine run
>normally.  Single-bit errors will be corrected automatically, with a
>note from the O/S (as reported by the hardware) when this happens.  The
>`address' and `syndrome' bits identify exactly which chip is failing,
>although the only way to go from address+syndrome to chip is via the
>manufacturer's tables (or trace the board! ... not for me, thanks),
>which are sometimes hard to find.

On a high reliability system we designed, we had an ECC error "gleaner"
which would read and write successive memory locations in order to correct
soft single bit errors before alpha particles (or whatever) changed them 
into double bit errors and made them uncorrectable.

Is there a more proper name for this?  To me a "gleaner" brings to mind
someone working at the feet of the grim reaper.  Not too pleasant a 
thought.

-Jack
-- 
Jack Bonn, <> Software Labs, Ltd, Box 451, Easton CT  06612
uunet!swlabs!jack (UUCP)	jack%swlabs.uucp@uunet.uu.net (INTERNET)