Path: utzoo!attcan!uunet!husc6!bloom-beacon!oberon!eve.usc.edu!mlinar
From: mlinar@eve.usc.edu (Mitch Mlinar)
Newsgroups: comp.misc
Subject: Re: Mythical microprocessors
Message-ID: <11419@oberon.USC.EDU>
Date: 7 Aug 88 20:18:10 GMT
References: <677@buengc.BU.EDU> <79700005@p.cs.uiuc.edu>
Sender: news@oberon.USC.EDU
Reply-To: mlinar@eve.usc.edu (Mitch Mlinar)
Organization: University of Southern California, Los Angeles, CA
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In article <79700005@p.cs.uiuc.edu> gillies@p.cs.uiuc.edu writes:
>
>I heard that the (oriental) designer of the Z80 and Z8000 did most of
>the design in his head.  That is, he understood almost the entire CPU
>and its layout in VLSI.  I think he left from Zilog before the Z80,000
>was complete.  Had he stayed (to influence the Z80,000 design), the
>chip might have been more successful.
>

The name of the designer escapes me right now, but I believe he was from
India.  Also, he laid out the Z80 and Z8000 primarily using RANDOM LOGIC.  He
was *very* good at it, but also realized that regular structures like PLAs,
etc.  would be required for the next generation.  The Z8000 took a *lot* of
man-months in comparison to other CPUs of that time due to the random logic,
but was faster because of it.

To this day, I know of no synthesis tools for CPUs which can handle timing
generators (the method used in the Z80 and Z8000).  Current chips are all
micro/nanocontrollers and/or PLA table driven.  Timing generators ARE faster
for a comparable size design, but the complexity versus speed gain is just
not worth it.  Then, there is the issue of verification.  Ugh!

-Mitch