Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ucbvax!UB.CC.UMICH.EDU!Todd_A._Bakal
From: Todd_A._Bakal@UB.CC.UMICH.EDU
Newsgroups: comp.sys.apple
Subject: Using Caches to avoid Mhtz limitations
Message-ID: <1758548@ub.cc.umich.edu>
Date: 3 Aug 88 01:36:52 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
Lines: 16

Without individually responding to many of the comments concerning
the speed of a gs+ being potentially held back by the 150 ns
memory chips, it seems to me that a 64K cache of fast static ram
(like in some of the killer 386's) would address many of these
concerns.  I believe that the Zip Chip has an 8k cache for this
purpose since most 6502 code runs in short loops.  I think that one
bank out of 16 (1 meg) would make the current fast ram / slow ram
scheme look silly.  Hypothetical?  Sure, why not.  But, it's at least
one response to those who would continue to write off the Apple II as
long past dead.
 
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     Todd A. Bakal                        There's a sucker born every minute.
     U of M Apple User's Group            That makes 5.256E+4 a century!
     Ann Arbor, Michigan
     ARPA: Tabakal@ub.cc.umich.edu        BITnet: Tabakal@UMICHUM