Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!nrl-cmf!cmcl2!adm!smoke!gwyn
From: gwyn@smoke.ARPA (Doug Gwyn )
Newsgroups: comp.sys.apple
Subject: Re: clock speeds/RAM/drives
Message-ID: <8303@smoke.ARPA>
Date: 3 Aug 88 04:47:11 GMT
References: <8808012324.aa05390@SMOKE.BRL.MIL>
Reply-To: gwyn@brl.arpa (Doug Gwyn (VLD/VMB) <gwyn>)
Organization: Ballistic Research Lab (BRL), APG, MD.
Lines: 10

In article <8808012324.aa05390@SMOKE.BRL.MIL> AWCTTYPA@UIAMVS.BITNET ("David A. Lyons") writes:
>Since during any given memory access only ONE of the 4 groups of
>chips is being read from, we can take the opportunity to pre-fetch,
>or at least START to pre-fetch, the next 3 bytes from the other 3
>groups of chips.

Interleaving memory is of course one of the standard ways to increase
its effective transfer rate.  You do need to worry about synchronization
issues, since much memory access is not sequential.  A generally more
effective approach is to has a modest high-speed cache.  On the IIGS
the graphics page might be treated as special "write-through" addresses.