Path: utzoo!attcan!uunet!husc6!linus!dartvax!eleazar.dartmouth.edu!stevel
From: stevel@eleazar.dartmouth.edu (Steve Ligett)
Newsgroups: comp.sys.ibm.pc
Subject: cycle time vs. access time (was: RAM speed per clock rate)
Message-ID: <9703@dartvax.Dartmouth.EDU>
Date: 8 Aug 88 14:57:54 GMT
References: <22faf142@ralf>
Sender: news@dartvax.Dartmouth.EDU
Reply-To: stevel@eleazar.dartmouth.edu (Steve Ligett)
Organization: Dartmouth College, Hanover, NH
Lines: 38

In article <22faf142@ralf> Ralf.Brown@B.GP.CS.CMU.EDU writes:

N.B. The whole original article deleted here, and most of the reply from
Ralf.Brown.

> Dynamic RAMs require a memory
> cycle time of twice the access time (due to setup and recovery times).

I've seen this asserted several times, and maybe it's a convienent
approximation.  But it's not exactly correct.  The cycle times are not so
simply related to the access times.  There is no simple equation that
applies to all memory chips, from any maker, in any density, in any
technology.

You have to read the memory data sheets to get the two numbers, and then
you'll have to read the data sheets from your microprocessor maker, and
account for the time taken by the "glue" logic on the board to come up
with required memory speed.  Sometimes the access time will be the
limiting factor, and sometimes the cycle time will be.

With that as disclaimer, here is a table of access and cycle times for
generic (dynamic ram) chips --

access   cycle
time     time
200 ns   330 ns
150 ns   260 ns
120 ns   220 ns
100 ns   190 ns
 85 ns   165 ns

Some of the old chips had longer cycle times for these access times, and
I've seen data sheets for some Hitachi products that have faster cycle
times for these access times.  Also, remember that these are memory chip
times, not memory system times.

   Steve Ligett     steve.ligett@dartmouth.edu or
(decvax harvard ihnp4 linus)!dartvax!steve.ligett