Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-tis!ames!oliveb!pyramid!ctnews!starfish!cdold
From: cdold@starfish.Convergent.COM (Clarence Dold)
Newsgroups: comp.sys.ibm.pc
Subject: Re: RAM speed per clock rate
Summary: The CPU assumes a RAM speed
Message-ID: <623@starfish.Convergent.COM>
Date: 8 Aug 88 22:53:30 GMT
References: <22faf142@ralf>
Organization: Convergent Technologies, San Jose, CA
Lines: 41

>         1/clock speed * memory_access_clocks / 2 = RAM speed in ns
> Actually, a 4.77MHz 8088 would let you use 400 ns parts! (if any existed)
> }     8Mhz clock:        1 /  8,000,000 = 125 nS or faster.
I am glad that someone typed in a reasonable response to this.
I feel guilty over having watched so much misinformation go by, but my company 
deals in proprietary hardware, I'm not sure how PC-compatible some of these 
details are.  On a 80186 - 8 MHz processor, in production since 1983, we use 
120nSec parts with no wait states, that coincides with your chart.
The CPU can't just grab data from a Dynamic RAM (DRAM).
On a system with multiple DMA masters, there is a lot of arbitration to wade 
through.  In addition to that, there is settling time on various gates 
to contend with.
At T0, the CPU will drive Status bits S2-S0 to indicate a RAM activity.  
Address lines will also be presented.  Arbitration may or may not ocurr.  
ALE will be asserted, indicating that bits on the address/data bus are stable.

64k DRAMs require 16 address bits, but only have 8 address pins.
256k DRAMs need 18 bits, provide 9 pins.
First the 9 Least significant bits are sent, along with RAS (Row Address Strobe)
about 155nSec into the cycle.  The high order bits are applied to the same pins
and Column Address Strobe (CAS) is applied at about 185nSec into the cycle.
**********
A 120nSec rated chip is guaranteed to have stable data on its output
120nSec after this RAS/CAS cycle is started.
**********
There is no handshake coming back from the chip.  Your system will not 'just run slower' with RAM that is too slow!!!  After a calculated length of time, 
approximately 275nSec total on our system, you assume data is stable, and clock it in by presenting ARDY to the CPU!!!

If your chips are slow, data won't be there.  Parity might catch the problem,
but if you drop two bits, it will get by the parity circuit.
The 80186 will latch data on the next trailing edge after finding ARDY.
You might be able to set switches to add wait states to RAM access.  This 
will change the calculated time before ARDY is generated.
If you're lucky enough to squeak by with some underated chip, you are just
that... lucky.  Temperature and the whims of nature might get a chip.

I think PC's also typically define additional wait states on accesses
to the expansion bus, so what won't work on the motherboard might work
on an expansion card, but that is a wild guess, and doesn't belong in this
posting, which is otherwise legitimate.

I feel much better now.