Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!amdahl!nsc!taux01!cjosta
From: cjosta@taux01.UUCP (Jonathan Sweedler)
Newsgroups: comp.sys.nsc.32k
Subject: Re: Some architecture questions
Summary: series 32k disables interrupts after an interrupt
Keywords: interrupts
Message-ID: <877@taux01.UUCP>
Date: 7 Aug 88 05:49:47 GMT
References: <5980003@hpccc.HP.COM>
Reply-To: culberts@hpccc.HP.COM (Bruce Culbertson)
Organization: National Semiconductor (Israel) Ltd.
Lines: 20

In article <5980003@hpccc.HP.COM> Bruce Culbertson writes:
>I recently noticed a few features of the NS32000 architecture which
>I do not understand.   Maybe someone could enlighten me.
>
>Second, why don't the traps clear the interrupt enable flag? 

Section 6.8.1 of the _Series 32000 Instruction Set Reference Manual_
describes the "Maskable/Non-Maskable Interrupt Sequence."  Step 2 is:
"Copy the Processor Status Register (PSR) into a temporary register,
then clear PSR bits S, U, T, P and I."  The I bit in the PSR is the
Interrupt Enable bit.  When the I bit is cleared, only Non-Maskable
interrupts are accepted.  Thus, after an interrupt is received, a 32000
series chip will ignore Maskable interrupts until told to do otherwise.
And, of course, the RETT (Return from Trap) instruction restores the
value of the PSR (not including the P bit) to its value before the
interrupt.  Thus, an interrupt scheme such as the one you proposed,
is indeed possible in the 32000 series architecture.
-- 
Jonathan Sweedler    ======    National Semiconductor  (Israel)
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