Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-lcc!ames!pacbell!belltec!dar
From: dar@belltec.UUCP (Dimitri Rotow)
Newsgroups: comp.unix.microport
Subject: Re: HELP! Floating Point Problems
Summary: Let's be precise about Erratum21
Message-ID: <252@belltec.UUCP>
Date: 8 Aug 88 16:02:26 GMT
References: <2424@inco.UUCP> <371@uport.UUCP> <248@belltec.UUCP> <387@uport.UUCP>
Organization: Bell Technologies, Fremont, CA
Lines: 41

In article <387@uport.UUCP>, plocher@uport.UUCP (John Plocher) writes:
> In article <248@belltec.UUCP> dar@belltec.UUCP (Dimitri Rotow) writes:
> >In article <371@uport.UUCP>, keith@uport.UUCP (Keith Hankin) writes:
> >> 2.  There is a known problem (Called Errata #21 by Intel) with the 80386
> >...
> >This is an inaccurate description of Erratum 21:  it has nothing to do with
> >DMA at all.
> 
[ John quotes some folks on Erratum 21 ]
> 
>     "The problem occurs when four conditions are met simultaneously ...
>     The first condition is that demand paged virtual memory must be active.
>     The second is that the system must be using a DMA oriented peripheral ...
>     The third condition is that the system must have a 387 chip installed,
>     and in use, and the fourth is that the 80386 must be in a wait state."

This is not a precise way to characterize the Erratum at all:  that's why
Intel publishes the precise, written descriptions to the length they do.  
DMA is not the culprit.  If the 386 sees a hold request (for example, in 
*refresh* time, not just DMA or other phenomena), then one of the necessary
conditions for Erratum 21 occurs.  Note that memory refreshes happen almost
continually (every 14 us or so) whereas by that reference scale DMAs occur
at nearly geologic intervals.  That's why it's so misleading to characterize
the Erratum as being a DMA or system level peripheral problem ... it's 
pointing you in the wrong direction by three or more orders of magnitude.

Note that the Erratum occurs with the *287* as well as a 387, and it can
be turned on and off (machine architecture permitting) depending on how 
the uppermost address lines are set.  The citation of "wait state" is 
misleading, since even a "zero wait state 386" will encounter Erratum 21
with pre D stepping 386 parts. 

> Granted, this is a bit different from the Official Intel Errata 21 publication
> that you and I know so well, but if you think about it, the physical
> conditions are similar.

I appreciate the spirit, but to cite a subset manifestation of Erratum 21 as
defining the problem can cause real difficulty among people trying to cope 
with it.  After a year's experience with the issue, we see no reason to doubt
the accuracy of Intel's publication.

- Dimitri Rotow