Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!vsi1!wyse!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: [really: IQFs]
Message-ID: <2905@winchester.mips.COM>
Date: 26 Aug 88 01:48:52 GMT
References: <941@srs.UUCP> <408@ma.diab.se> <2693@winchester.mips.COM> <99@taux02.UUCP>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 24

In article <99@taux02.UUCP> yuval@taux02.UUCP (Gideon Yuval) writes:
>In article <2693@winchester.mips.COM> mash@winchester.UUCP (John Mashey) writes:
>>2) It might be reasonable to compute IQFs, but you need access to very
>>good architectural simulations.  It is very hard to measure them by running
>>benchmarks.
>
>Ori Danieli's M.Sc. Thesis (Tel Aviv University, 7/88) has  some  simulations
>on  two  architectures:  one  is  almost  the full NS32K architecture (except
>that memory-to-memory operations are not there); the other  is  a  load/store
>RISC  subset  of the NS32K architecture. He finds a 12% average difference in
>the number of  instructions  needed  to  run  the  same  program.  In  the  5
>programs  run,  this  difference was 7% for DC, PTC (a Pascal-to-C converter)
>and SORT, 17% for GREP, and 23% for SED.

Interesting numbers.  Please say some more on methodology, if possible,
and what sort of compiler technology was being used.

I think this is saying that deleting the non-RISC-subset adds 12%
in number of instructions.  Did the thesis say anything about
total cycle counts (i.e., incl. memory system?)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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