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From: scott@labtam.OZ (Scott Colwell)
Newsgroups: comp.arch
Subject: Re: memory speed & futurology
Summary: comments and speculation
Message-ID: <891@labtam.OZ>
Date: 26 Aug 88 06:16:18 GMT
References: <2179@ditmela.oz>
Organization: Labtam Limited., Melbourne, Australia
Lines: 62

In article <2179@ditmela.oz>, george@ditmela.oz (George michaelson) writes:
> (2)	main memory gets 6 times faster and 8 times cheaper. cache gets
> 	2-3 times faster and 8 times cheaper. Thus their speeds almost
> 	converge. Does that make cache sufficiently unattactive to stop 
> 	being used?
> 
> 	-price/speed ratio looks ugly (twice the cost for saving 5-10ns)
> 	-overall access speed to memory is 2 X current speed to cache so
> 	for existing processor architectures you can possibly do without it
> 	unless there are `logical' reasons for using cache other than
> 	buffering for slower memory.

	There are two major factors in the access times of memory
	systems. The actual speed of the memory devices and the overheads
	associated with controlling them. (i.e. the time taken to drive
	address lines to stable final values etc.) Caches are typically
	fewer chips, simpler to control (no muxed addresses) and closely
	coupled to the CPU. These issues probably won't change and hence
	caches will remain faster than main memory (even if the same RAM
	chips are used for both). (And main memory will usually have either
	a bus or switching network between it and the CPU, hence more
	delay).

	Main memory is accessed by more than just the cpu in current
	machines. DMA and other processors need access to perform I/O,
	and in multiprocessors, the main memory is often the point
	of sharing. This implies that a very important parameter for
	main memory is the access latency (how long it will take for
	the main memory to become available for a given master). This
	is where caches are also useful, they reduce the amount of
	traffic that hits the main memory.
	(From the above it isn't clear if you know this. If so, sorry)

> (3)	do the new speeds still look good alongside predicted clock speeds
> 	for CPU or do we have another development lag here?

	The current crop of SRAM at the moment is not really up to the
	demands of the new processors being touted for release in
	calendar year '89 (if your criterion is zero waits states).

	80386 @ 20MHz requires 35ns SRAM.
		25MHz requires 30ns SRAM.
		32MHz requires ??
		faster ??
	Admittedly the 80386 makes more demands on memory than most
	of the current CPUs.

> (5)	do we start to get 32/64Mb by default in our workstations? 
> 	does the opsys change its memory usage when that much memory
> 	is around? 

	Using 1Mx1 chips and assuming two way interleave with 32bit
	memory the minimum configuration possible is 8Mbytes. If we
	assume 4Mx1 then the minimum is 32Mbytes. (I hope they bring
	out the x4 parts first this time :-)

	Scott
-- 
Scott Colwell			ACSnet:	scott@labtam.oz
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