Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!amdcad!weitek!krish
From: krish@weitek.UUCP (Krishnan Sridhar)
Newsgroups: comp.arch
Subject: RISC
Keywords: Just what the heck is it, anyway?
Message-ID: <707@jetsun.weitek.UUCP>
Date: 26 Aug 88 23:32:11 GMT
Organization: WEITEK Corporation, Sunnyvale CA
Lines: 29


Several articles have been posted in this group in the recent past comparing
the performance of certain benchmarks on different types of machines, most 
notably RISC machines.

Just what EXACTLY is RISC? I know it's an acronym for Reduced Instruction Set
Computer i.e., the intruction set is a lot simpler and smaller and therefore,
can be executed directly in hardware much faster. I am also aware of the
concept of register file windows (from RISC II - was it GOLD or BLUE or
neither?). Apart from these two concepts, are there any others unique to RISC
architecture? Frequently, I hear the term "Load-Store Architecture" applied
specifically to RISC machines. What *exactly* does it mean and what are it's
implications in the architecture of a machine?

Much has been talked about RISC in the past year or so, with the introdution
of RISC processors from SUN, MIPS, MOTOROLA etc. Is the concept of RISC really
that revolutionary, or is it just another infinitesimal addition to the list
of buzzwords already floating around?

Please note that I am not trying to critique RISC architecture in any way. My
exposure to RISC is limited and I would really appreciate getting responses to
my questions from people out there in the arch.comp land.

Thanks much in advance.

P.S.   Also a list of references and/or books on RISC will be appreciated.

       My apologies, if this topic has already been beaten to death; I am
       fairly new to this net.