Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!zodiac!joyce!sri-unix!garth!walter
From: walter@garth.UUCP (Walter Bays)
Newsgroups: comp.arch
Subject: Re: Sun 4 MIPS rating [really: IQFs]
Message-ID: <1305@garth.UUCP>
Date: 26 Aug 88 16:35:48 GMT
References: <941@srs.UUCP> <408@ma.diab.se> <2693@winchester.mips.COM> <99@taux02.UUCP>
Reply-To: walter@garth.UUCP (Walter Bays)
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 28

>(John Mashey) writes:
>>2) It might be reasonable to compute IQFs, but you need access to very
>>good architectural simulations.

In article <99@taux02.UUCP> yuval@taux02.UUCP (Gideon Yuval) writes:
>Ori Danieli's M.Sc. Thesis (Tel Aviv University, 7/88) has  some  simulations
>on [NS32K versus a RISC subset of NS32K]

This seems very difficult to me, since you can only measure the
compiler + instruction set, not just the instruction set.  (Or if you
resort to hand-coded assembler, you measure programmer + instruction set.)
Even if you use the same compiler front-end, the differences in code
generators will influence the results.  A RISC code generator that is a
modified version of a CISC code generator probably won't do as good a
job of register allocation, register targeting, and handling intermediate
values.  A CISC code generator that is a modified version of a RISC code
generator will probably use mostly a RISC subset of the instructions.

This is not a criticism of Mr. Danieli's thesis, which I have not read.
It's now on my "read sometime" list.  If you tell me he went to great
lengths to address the compiler effects, it goes on my "read as soon
as I can find a copy!" list.
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