Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!apple!voder!pyramid!vsi1!wyse!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: How the Japanese will win the MIPS wars with SPARC
Message-ID: <3026@winchester.mips.COM>
Date: 2 Sep 88 17:35:26 GMT
References: <58@zeno.MN.ORG>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 60

In article <58@zeno.MN.ORG> gene@zeno.UUCP (Gene H. Olson) writes:
	Gene states a number of authoritative-sounding facts,
	followed by some strong prognostications.
	Some of the facts are wrong, and need correction.
	Prognostications about the future must await the future;
	the best way to treat them is to save a copy, and look
	at it after time has passed, and more data available.
	As a service to the net, I'll keep a copy, so others need
	not do so, and repost it, adding lists of design wins;
	maybe every 6 months or so.
>For some time now, I have been studying the available RISC
>architectures and have come to (what is to me) a startling
>and inescapable conclusion.   The Japanese will win the
>RISC wars, they will win it with SPARC because SPARC will
>be cheaper, and will have equal or better performance than
>the others.

You might want to study a little harder.  You may not have noticed
that the 16.7MHz R2000 in the M/120 generally runs real programs 1.5X
faster than the 16.7MHz SPARC in the Sun-4/200; but then it costs less, too.
That's the current state of the world.


>The logic is as follows:
>
>*	The Motorola, Intel, MIPS, SPARC, HP, and IBM RISC
>	architectures are incredibly similar.  In their basic
>	instruction sets, none of them has any significant
>	advantages over the other.
>
>	All of them have a 32 bit register-to-register architecture.
>	All of them have between 16 and 32 addressible registers.
There's a difference between 16 and 32.
>	All of them are capable of 1.1 -> 1.5 cycles per instruction.
There's also a difference between 1.1 and 1.5.
>	Lets face it guys, you just can't do that much different
>	with hardware instruction decoding.
Wait and see.
>*	What ultimately will make these machines faster is memory
>	technology.   Particularly cache memory technology.
This is probably true.
>	The Japanese know memory technology very well.
>
>*	All of these architectures, except SPARC is proprietary.
You also may not have noticed that there are already 3 suppliers
of pin-compatible MIPS chips.
>*	The Japanese will embrace SPARC with a singular ferocity.
Wait and see.

>*	Driven by price realities in the market, OEMs throughout the
>	world will choose Japanese SPARC processors.
Wait and see.

>*	Japanese SPARC will predominate.
Wait and see.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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