Path: utzoo!utgpu!water!watmath!clyde!att!pacbell!lll-tis!helios.ee.lbl.gov!pasteur!zabriskie!spp
From: spp@zabriskie.uucp (Steve Pope)
Newsgroups: comp.lsi.cad
Subject: Re: DRC for KIC
Message-ID: <5210@pasteur.Berkeley.EDU>
Date: 24 Aug 88 23:55:33 GMT
References: <8808242141.AA01052@columbia.edu>
Sender: news@pasteur.Berkeley.EDU
Reply-To: spp@zabriskie.UUCP (Steve Pope)
Organization: Postgres Research Group, UC Berkeley
Lines: 25

In article <8808242141.AA01052@columbia.edu> yk@SWISS.CTR.COLUMBIA.EDU (Yoshihito Koya) writes:
>I am looking for a design rule checking program for KIC2, layout editor.
>I tried to get LYRA layout-rule checking program from Berekeley Industrial
>Liason Office but they do not give it out anymore.  

Lyra last appeared on the Berkeley VLSI distribution in about 1985.
We have been using lyra and kic2 since about that time.  Both lyra
and the Franz Lisp translator (needed to run lyra) have required a 
certain amount of maintenance to keep up with SUN's operating system
upgrades, however, the combination is quite workable.  

Since that time, lyra has been removed from the Berkeley distribution, 
and the public-domain Franz Lisp is no longer distributed by Berkeley as
well.  

Lyra is slow -- e.g., about 4 CPU-days on a SUN-3 to check a 65,000
transistor chip.  Just about any other DRC program, including magic,
will probably run much faster.  

> Also, if anyone knows any other medium-to-low priced
> layout-checking program, please let me know.  I appreciate your help.

Let me know too!

steve pope (...ucbvax!spp)