Path: utzoo!attcan!uunet!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.gwd.tek.com (Andrew Klossner)
Newsgroups: comp.sys.m68k
Subject: Re: quad-aligning the 68020 stack
Message-ID: <10303@tekecs.TEK.COM>
Date: 25 Aug 88 19:40:03 GMT
References: <4486@cbmvax.UUCP> <4549@cbmvax.UUCP>
Sender: andrew@tekecs.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 15

[]

	"If you extend the internal Harvard architecture of the 68030
	to two external 32 bit buses, one for I, one for D, you could
	probably get a real performance improvement.  External caches
	could funnel both buses together to form a single 32 bit system
	bus, much like the 88k does."

To finish the thought: if you implement 88k-like caches, you'll have
16-byte cache lines, and you'll get a slight performance improvement if
you align the stack frame to a multiple of 16 bytes (because your stack
frame will use the smallest possible number of cache lines).

  -=- Andrew Klossner   (decvax!tektronix!tekecs!andrew)       [UUCP]
                        (andrew%tekecs.tek.com@relay.cs.net)   [ARPA]