Path: utzoo!lsuc!utgpu!water!ylfink
From: ylfink@water.waterloo.edu (ylfink)
Newsgroups: ont.events,uw.talks
Subject: Symbolic Processing Using RISCs: SPUR A Retrospective on the Cache      Controller Development.
Keywords: Garth Gibson, Wed., Sept. 7/88, 3:30 PM, MC 6091A.
Message-ID: <1808@water.waterloo.edu>
Date: 1 Sep 88 18:40:36 GMT
Distribution: ont
Organization: U of Waterloo, Ontario
Lines: 37



DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES

COMPUTER ARCHITECTURE/PERFORMANCE ANALYSIS
AND OPERATING SYSTEMS SEMINAR

                    -  Wednesday, September 7, 1988

Garth  Gibson, University of California, Berkeley, will
speak  on  ``Symbolic  Processing  Using RISCs:  SPUR A
Retrospective on the Cache Controller Development''.

TIME:                3:30 PM

ROOM:              MC 6091A

ABSTRACT

SPUR   is  a  multifaceted  Berkeley  project  that  is
building a loosely coupled network of high-performance,
shared-memory multiprocessors with hardware support for
LISP  and  cache coherency.  Each processor is composed
of  a 128KB cache and three custom CMOS chips: a CPU, a
floating  point  coprocessor,  and  a cache controller.
Advanced  features  of  the  cache  controller chip are
in-cache   address   translation   and  hardware  cache
coherency.

In  this talk I will introduce the architecture of SPUR
and  describe  some  of  our  experiences with complete
system  building  in a university.  I will focus on the
project  stages  of specification, simulation, testing,
and  system integration by following the development of
the cache controller.