Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!gaas!garner
From: garner@gaas.Sun.COM (Robert Garner)
Newsgroups: comp.arch
Subject: Re: Are all RISCs the same?
Keywords: SPARC, RISC
Message-ID: <67551@sun.uucp>
Date: 8 Sep 88 23:57:43 GMT
References: <58@zeno.MN.ORG> <6903@aw.sei.cmu.edu> <22860@amdcad.AMD.COM> <6930@aw.sei.cmu.edu>
Sender: news@sun.uucp
Reply-To: garner@sun.UUCP (Robert Garner)
Organization: Sun Microsystems, Mountain View
Lines: 30

>  But what true real time systems want, in most cases, is interrupts
>  that change the scheduler state, and hence that are followed by a
>  true context switch.
>  ...
>  But using the normal register window for interrupts seems crazy:
>  if the interrupt occurs at the wrong call depth
>  (1/4 of the time, say) then responding to it will take several times as
>  long, since 128 (or whatever) registers will be spilled to give it a
>  window of 32, of which it might use 4.  This is negative leverage with a
>  vengeance!

assuming that an interrupt always causes a context switch; then, in
order to achieve minimal context switching latency, just save a SINGLE window
on a context switch (16 registers in SPARC).  the rest can be saved later.
(note that the work of window saves, which write procedure PC,
FP, and stack data into memory, must be accomplished in all architectures
at SOME point in time between context switches.)

also, the SPARC register windows can be managed differently in a particular
real-time application:  every other window in SPARC can be marked invalid
in the privileged Window Invalid Mask register.  this yields
"number-of-windows/2" 40-register groups, where each group comprises
32 registers plus 8 trap handler registers dedicated to a real-time task.
tasks are protected from each other via the Window Invalid Mask.  changing the
Current Window Pointer accomplishes a process switch among the active groups.
(of course, processes in this scheme are compiled with a "single, traditional
register set" model.)

	- rg