Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!amdcad!news
From: news@amdcad.AMD.COM (Network News)
Newsgroups: comp.arch
Subject: Re: Are all RISCs the same?
Message-ID: <22877@amdcad.AMD.COM>
Date: 9 Sep 88 02:39:23 GMT
References: <58@zeno.MN.ORG> <6903@aw.sei.cmu.edu> <22860@amdcad.AMD.COM> <6930@aw.sei.cmu.edu> <67551@sun.uucp>
Reply-To: tim@crackle.amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Sunnyvale CA
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In article <67551@sun.uucp> garner@sun.UUCP (Robert Garner) writes:
| also, the SPARC register windows can be managed differently in a particular
| real-time application:  every other window in SPARC can be marked invalid
| in the privileged Window Invalid Mask register.  this yields
| "number-of-windows/2" 40-register groups, where each group comprises
| 32 registers plus 8 trap handler registers dedicated to a real-time task.
| tasks are protected from each other via the Window Invalid Mask.  changing the
| Current Window Pointer accomplishes a process switch among the active groups.
| (of course, processes in this scheme are compiled with a "single, traditional
| register set" model.)

This scheme is also present in the Am29000 register model, since the
register file can be protected in groups of 16 registers.  However,
current compilers support only the stack-cache model, since it provides
the highest performance in most applications.

Do the SPARC compilers support both stack-cache and register-bank
calling conventions?


	-- Tim Olson
	Advanced Micro Devices
	(tim@crackle.amd.com)