Path: utzoo!attcan!uunet!lll-winken!lll-lcc!ames!pasteur!ucbvax!unisoft!paul
From: paul@unisoft.UUCP (n)
Newsgroups: comp.arch
Subject: Re: Are all RISCs the same?
Message-ID: <1278@unisoft.UUCP>
Date: 12 Sep 88 16:34:49 GMT
References: <58@zeno.MN.ORG> <6903@aw.sei.cmu.edu> <22860@amdcad.AMD.COM> <6930@aw.sei.cmu.edu> <22890@amdcad.AMD.COM>
Reply-To: paul@unisoft.UUCP (Paul Campbell)
Lines: 38

In article <22890@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
>+---------------
>
>Well, I don't know what machine you have in mind, but for the Am29000
>(which has 128 "local" registers) it doesn't work that way. The 29k
>has completely *variable*-sized register windows, and you spill exactly
>what is needed.  Thus, an interrupt sequence which uses 4 local registers
>will spill/fill (save/restore) exactly 4 of them, and an interrupt sequence
>which uses 37 registers (because of subroutine call depth or whatever)
>will save/restore exactly 37.
>
 	.....
>
>Rob Warnock
>Systems Architecture Consultant
>


Rob of course didn't tell you how long it actually takes to burst transfer
all 192 registers to memory (if you really do have to save them all ....)


	at 30MHz (33nS/cycle) 192*0.033 -> 6.3 uS (6.4uS actually if
		you count a 2-3 cycle burst setup time)

not too bad!! the typical time a kernel spends looking for the next process
to execute plus and changing the memory map on process switch easily
dwarfs this (hell interrupt acknowledge time on most modern buses is around
1uS). Maybe a 4-5 years from now this will become a big issue but by then
the silicon will be that much faster anyway

		Paul Campbell


-- 
Paul Campbell, UniSoft Corp. 6121 Hollis, Emeryville, Ca
	E-mail:		..!{ucbvax,hoptoad}!unisoft!paul  
Nothing here represents the opinions of UniSoft or its employees (except me)
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