Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!amdcad!ames!ncar!noao!asuvax!nud!df From: df@nud.UUCP (Dale Farnsworth) Newsgroups: comp.arch Subject: Re: Explanation, please! Message-ID: <1276@nud.UUCP> Date: 13 Sep 88 17:16:47 GMT References: <638@paris.ics.uci.edu> <189@bales.UUCP> <10329@tekecs.TEK.COM> <760@bnr-rsc.UUCP> Reply-To: df@nud.UUCP (Dale Farnsworth) Organization: Motorola Microcomputer Division, Tempe, Az. Lines: 14 Mark MacLean (mark@bnr-rsc.UUCP) writes: > Is it not possible to unroll the loop into an inline stream of instructions > (if the length is small and known at compile time) to produce an instruction > sequence which could perform a memory access every cycle? If not, why not? > It would seem very un-RISCy if the 88000 was unable to do this. Of course, it is possible to do a memory access every cycle on the MC88100 (with a 2 cycle pipeline startup delay on the first memory access), but at 25 MHz, your memory will have to have an effective cycle time of 40 nS. If memory is slower, the processor can increment pointers and check termination conditions while waiting for memory. -Dale