Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!mailrus!cornell!rbrown
From: rbrown@svax.cs.cornell.edu (Russell Brown)
Newsgroups: comp.sys.atari.8bit
Subject: Re: 6502 timing question
Message-ID: <20910@cornell.UUCP>
Date: 9 Sep 88 20:35:37 GMT
References: <8809091641.AA15253@ucbvax.Berkeley.EDU>
Sender: nobody@cornell.UUCP
Reply-To: rbrown@svax.cs.cornell.edu (Russell Brown)
Organization: Cornell Univ. CS Dept, Ithaca NY
Lines: 34

In article <8809091641.AA15253@ucbvax.Berkeley.EDU> BIW109@URIMVS.BITNET writes:
>
>  I have a question on the timing of the 6502.  Which requires more
>time, an LDA, or an STA?  The reason that I ask is that I am working
>on an interfacing project, and am running into problems.  I think that
>the problem might be caused by too much delay time in the interface
>its self.  The problem is that I am able to read from an external port
>(in this case, an A/D converter) with 100% accuracy, but I an unable to
>write to another port (a D/A converter made from an 8-bit latch and an
>R-2R resistor ladder).  Writes to the D/A converter are sucessful only
>about 10% of the time.  The interface circuit introduces the same delay
>before activating each port.  I think that I am able to read ok because
>on the fact that the cpu allows at least 250ns for the memory (or what
>ever is on the bus) to respond.  Can anyone tell me how much time the
>cpu allows for memory (or what ever) to latch a byte from the bus?
>

	The timing for reading and writing bytes to memory is roughly the
same.  In either a store or a fetch, one memory cycle is used (during the
first part of the cycle, phase-1, an address is placed on the bus by the
processor.  Devices connected to the bus decide during this time if they
are being addressed; if the chip enable is set, then depending on the state
of the R/W' line, the enabled device either stores what it finds on the
data bus during phase-2, or outputs information onto the bus).  There are
a number of signals which must be dealt with properly; if you are having
difficulty on writes, you might check that data from the bus is getting
clocked into your latch during phase-2 proper (i. e. the information actually
has time to settle before you read it -- this would be a case of reading
into the latch too quickly, not too slowly.  Note that a latch is sufficiently
speedier than memory that the speed of your interface should not be a problem).

	My information is a little stale; also tinged with M6801 terms.  I
hope this is of some use to you.

						Russell g. Brown