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From: ehs@jumbo.dec.com (Ed Satterthwaite)
Newsgroups: comp.sys.atari.8bit
Subject: Re: 6502 timing question
Summary: check hold times too
Message-ID: <13342@jumbo.dec.com>
Date: 10 Sep 88 00:24:54 GMT
References: <8809091641.AA15253@ucbvax.Berkeley.EDU> <20910@cornell.UUCP>
Organization: DEC Systems Research Center, Palo Alto
Lines: 38

One other thought.

When I opened up my 800 a while ago, I found a Rockwell 6502B.  For write
data, Rockwell's specs for the B version provide a minimum hold time of 15
ns. from fall of phi2 (end of phase-2).  These timings are at the
processor chip pins.

If you are using a flow-through latch ('373 or similar), the data has to
be valid when the latch closes and has to remain so for, e.g., at least 20
ns (TI's specs for 74LS373).  In most designs, the write strobe is a gated
phi2.  So things are already problematical.  They will probably work
because the capacitance of the data bus is working for you and most TTL
parts I've encountered are considerably better than their specs, but ...

I have seen designs (gated phi2) in which there are more logic delays on
the write strobe than buffering delays in the data path.  This could push
things over the edge (data corrupted before latch closes) and account for
the marginal operation you observe.  If I recall correctly (I don't have
the schematics at hand), the system phi2 on an 800 might already be
leading the 6502's phi2 by the difference between two gate delays.  The
XLs and XEs actually use a customized 6502, which handles phi2 differently
and might be better or worse.  If you are right on the edge, going to a
74F latch might bail you out (hold time on a 74F373 is 3 ns, for example).
Bypass generously.  Also, hold times for edge-triggered flip-flops are
typically lower than for latches, but you don't get the flow-through and
you can't use the leading edge of phi2 (data not speced to be there yet).

Finally, I have seen MOS parts with internal latches that have very long
hold times compared to TTL.  If you're using such a part, simple
interfacing might just be incompatible with reliable operation.

I hope that some of this helps and that none of it is too misleading --
it's been a long time since I've looked at my Atari.  I suggest investing
in some schematics and data books if you can find them, then checking the
timing margins on all the relevant signals.

Ed Satterthwaite
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