Path: utzoo!attcan!uunet!husc6!mailrus!cornell!rbrown
From: rbrown@svax.cs.cornell.edu (Russell Brown)
Newsgroups: comp.sys.atari.8bit
Subject: Re: more info on my interfacing problem..
Message-ID: <21105@cornell.UUCP>
Date: 18 Sep 88 00:36:33 GMT
References: <8809152000.AA28912@ucbvax.Berkeley.EDU>
Sender: nobody@cornell.UUCP
Reply-To: rbrown@svax.cs.cornell.edu (Russell Brown)
Organization: Cornell Univ. CS Dept, Ithaca NY
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	The old Ataris run on the 1.79 MHz 6502B.  The 6502 clock setup
provides for a two part instruction cycle.  Information placed on the bus is
supposed to be valid for the duration of the appropriate part of the cycle
(address during phi-1, data during phi-2).  Phi-1 and phi-2 are approximately
equal, each accounting for about 40% of an instruction cycle (with the other
20% taken up by transitions -- phi-1 and phi-2 are nonoverlapping, so there's
some space between them).  My documentation isn't where I can get at it, so
I can't look up whether an instruction cycle takes 1/(1.79MHz) or
2/(1.79Mhz), but if we assume, for the moment, the former, then each phase
of the cycle lasts about 223 nanoseconds (if the assumption is incorrect,
then the cycle lasts some small integer (perhaps 2) times that long).  As I
said, this is not the final word, but I have confidence that it is no
shorter than this.